(a) Field of the Invention
The present invention relates to a semiconductor device including gate insulation films having different thicknesses. The present invention also relates to a method for forming such a semiconductor device.
(b) Description of the Related Art
Along with the developments of finer patterning and high-speed operation of semiconductor devices, a multi-functional semiconductor device, such as a system LSI, formed on a single semiconductor substrate is increasingly used for a variety of applications. In the system LSIs, a finer patterning technology using a STI (shallow trench isolation) structure is generally used. On the other hand, some techniques for the system LSIs use a fabrication process for forming gate insulation films having different film thicknesses for adapting the gate insulation films to different functions of the system LSIs.
In a typical STI structure, a problem of the step portion in the STI, known as a STI step problem, is known. The STI step is formed as detailed below. In general, a silicon oxide film formed within the shallow trench is subjected to an undesired etching during the etchings performed in the respective areas isolated by the shallow trench. The undesired etching generally causes a depression at the edge of the shallow trench, which forms the STI step. Once the STI step is formed at the edge portion of the isolation trench, the MOSFETs separated by the shallow trench suffer from an increase in the off-leakage current, whereby transistor characteristics are degraded. Patent Publication JP-A-2000-195969 describes a technique for preventing the degradation of the transistor characteristics by forming MOSFETs including gate insulation films having different thicknesses on a single substrate. FIGS. 1A to 1K show the consecutive steps of fabrication of such gate insulation films.
On a silicon (semiconductor) substrate 20, a silicon oxide film 21 is formed by a thermal oxidation technique, followed by deposition of a silicon nitride film 22 thereon, as shown in FIG. 1A, by using a CVD technique. On the silicon nitride film 22, a photoresist pattern (not shown) is formed, which has openings on the area for forming the shallow trench, by using a photolithographic technique. The silicon nitride film 22 is then subjected to patterning by anisotropic etching using the photoresist pattern as an etching mask, as shown in FIG. 1B. By using the thus patterned silicon nitride film 22 as an etching mask, the silicon oxide film 21 and the top portion of the silicon substrate 20 are selectively etched to form a shallow trench or isolation trench 23 having a depth of 100 to 500 nanometers (nm), as shown in FIG. 1C. The depth of the shallow trench 23 depends on the types of the circuit to be formed on the silicon substrate 20.
Subsequently, a silicon oxide film 24 having a thickness of around 300 to 1000 nm is deposited on the silicon nitride film 22 and within the shallow trench 23 by using a low-pressure CVD (LPCVD) technique. A CMP (chemical-mechanical polishing) process is then performed on the wafer by using the silicon nitride film 22 as a stopper, to remove a portion of the silicon oxide film 24 above the silicon nitride film 22, thereby leaving the lower portion of the silicon oxide film 24 within the shallow trench 23. Thereafter, the silicon nitride film 22 is removed by wet etching using hot phosphoric acid, as shown in FIG. 1D.
Subsequently, a silicon oxide film 25 having a thickness of around 3 to 15nm is formed on the surface portion of the silicon substrate 20 by using a thermal oxidation technique, as shown in FIG. 1E. Then, an ion implantation process is conducted for selectively implanting impurity ions such as boron or boron fluoride into an nMOS area, wherein nMOSFETs are to be formed, by using a mask, separately from an ion implantation process for implanting impurity ions such as phosphorous or arsenic into a pMOS area, wherein pMOSFETs are to be formed, by using another mask. Thus, well regions (not shown) are formed in the respective areas of the silicon substrate 20.
Thereafter, a silicon nitride film 26 is formed on the silicon oxide film 25, followed by forming a photoresist pattern 30 having an opening on a memory cell array area 29 among the whole areas including an logic circuit area 27, a sense amplifier area 28 and the memory cell array area 29, the memory cell array area 29 generally including MOSFETs having a larger thickness for the gate oxide films. The silicon nitride film 26 exposed from the opening of the photoresist pattern 30 is removed by etching, as shown in FIG. 1F. Further, ion-implantation is conducted for implanting impurity ions such as boron or boron fluoride through the opening of the photoresist pattern 30 while passing the thin silicon oxide film 25, thereby forming channel regions of memory cells in the memory cell array area 29.
The photoresist pattern 30 is then removed, followed by forming another photoresist pattern 31 having an opening on the sense amplifier area 28. The sense amplifier area 28 includes MOSFETs which have a gate insulation film having a thickness similar to the thickness of the gate insulation film of the MOSFETs in the memory cell area 29, and a threshold voltage different from the threshold voltage of the MOSFETs in the memory cell area 29. By using the photoresist pattern 31 as a mask, the silicon nitride film 26 in the sense amplifier area 28 is selectively removed, followed by implantation of impurity ions such as boron through the opening of the photoresist pattern 31 and the thin silicon oxide film 25, to form channel regions of the MOSFETs in the sense amplifier area 28, as shown in FIG. 1G.
The photoresist pattern 31 is then removed, followed by wet etching using the silicon nitride film 26 as a mask and hydrofluoric acid as an etchant, to remove the silicon oxide film 25 in the sense amplifier area 28 and the memory cell array area 29, which may be called herein thick-film areas. Another silicon oxide film 32 having a larger thickness than the silicon oxide film 25 in the logic circuit area 27 is then formed as a gate insulating film in the sense amplifier area 28 and the memory cell array area 29 by using an oxidation process, as shown in FIG. 1H. As shown in FIG. 1H, the silicon oxide film 25 and the silicon nitride film 26 are formed on the logic circuit area 27, which may be called herein a thin-film area, whereas the silicon oxide film 32 is formed on the thick-film 25 areas 28 and 29.
By using hot phosphoric acid as an etchant, the silicon nitride film 26 is removed in the logic circuit area 27, followed by forming another photoresist pattern 33 covering the active areas of the pMOSFETs in the thin-film area 27 and the thick-film areas 28 and 29. By using the another photoresist pattern 33 as a mask, impurity ions such as boron or boron fluoride are implanted into the active areas of the nMOSFETs in the logic circuit area 27 to form channel regions in the nMOSFETs in the logic circuit area 27. Similarly, by covering the active areas of the nMOSFETs in the thin-film area 27 and the thick-film areas 28 and 29, impurity ions are implanted to the active areas of the pMOSFETs in the logic circuit area 27, to form channel regions of the pMOSFETs therein. Thereafter, the silicon oxide film 25 in the logic circuit area 27 is removed, as shown in FIG. 11, followed by removal of the another photoresist pattern 33.
A silicon oxide film 34 having a thickness of about 4 to 7nm is then formed as a gate insulating film in the logic circuit area 27 by thermal oxidation, as shown in FIG. 1J. In this step, the silicon oxide film 34 is also formed on the preceding silicon oxide film 32 in the thick-film areas, or the sense amplifier area 28 and the memory cell array area 29, whereby all the channel regions and the gate insulating films are formed in the entire areas 27, 28 and 29.
Subsequently, in the case of nMOSFETs, a polysilicon film including impurity ions such as boron or boron fluoride at about 1xc3x971021/cm3 and having a thickness of about 50 to 100 nm is deposited by a CVD technique, followed by deposition of a metal silicide film such as a tungsten silicide film thereon by using a CVD or sputtering technique, and patterning thereof in combination with the polysilicon film to form a gate electrode 35. Further, ion-implantation is performed to implant phosphorous or arsenic into the nMOS area and boron or boron fluoride into the pMOS area at a dosage of about 3xc3x971013/cm2 and an acceleration energy of about 20 to 40 keV, thereby forming source/drain regions, as shown in FIG. 1K. Thereafter, a LPCVD step is conducted to form an interlayer insulation film having a thickness of about 200 to 600nm, followed by forming an interconnect pattern thereon.
The conventional technique as described above is directed to forming gate insulating films having two different thicknesses. It is recited in the publication that, by equalizing the numbers and the conditions of the removal steps for the silicon oxide films between the areas for which the thickness of the silicon oxide film is different, it is possible to prevent the in-trench silicon oxide film formed beforehand in the shallow trench from being excessively or differently etched, whereby the edge of the shallow trench has a uniform topology without a STI step.
Along with the development of higher functions for the semiconductor devices, it is desired to form gate insulating films having three or more different thicknesses in a single semiconductor device. More particularly, in a technique for fabrication of a system LSI, for example, it is desired to form different thicknesses of the gate insulating films for high-voltage MOSFETs in an I/O area, high-speed MOSFETs in a high-speed logic circuit area, and low-leakage current MOSFETs in a stand-by logic circuit area. In other word, it is desired to develop the technique for manufacturing MOSFETs having three or more different thicknesses for gate insulating films while assuring low-leakage current and excellent transistor characteristics for the MOSFETs.
In the technique described in the above publication, it is not recited to manufacture MOSFETs having three or more different thicknesses of the gate insulating films although it is recited to manufacture MOSFETs having two different thicknesses of the gate insulating films.
In addition, in the technique described in the above publication, the silicon oxide film 25 formed in common to the thick-film areas 28 and 29 and the thin-film area 27 is eventually removed, and instead, the silicon oxide films 32 and 34 are formed in the thick-film areas 28 and 29 whereas the silicon oxide film 34 is formed in the thin-film area 27. This necessitates removal of the silicon oxide films twice for the fabrication of MOSFETs having two different thicknesses of the gate insulating films.
Moreover, in the technique described in the above publication, a thin gate insulating film is formed in the thick-film areas 28 and 29, and then another thin gate insulating film is formed in the thin-film area 27. During the step for forming the thin gate insulating film in the thin-film area 27, the thin gate insulating films in the thick-film areas 28 and 29 are concurrently oxidized to form a thick gate insulating film. In such a process, however, the process conditions for forming the thin gate insulating film in the thin-film area 27 are inevitably limited by the process conditions for obtaining the final thickness of the thick gate insulating films in the thick-film areas 28 and 29. The process conditions used for forming the gate insulating films in the later or last step are thus complicated depending on the number of different thicknesses of the gate insulating films in a single LSI.
In view of the above, it is an object of the present invention to provide a semiconductor device having three or more different thicknesses of silicon oxide films in desired areas substantially without involving an increase in the gate-leakage current and an off-leakage current of the MOSFETs formed in the MOS areas.
It is another object of the present invention to provide a method for manufacturing such a semiconductor device.
The present invention provides, in a first aspect thereof, a method for fabricating a semiconductor device having thermal silicon oxide films having n different thicknesses, given n being an integer not smaller than three, the method including the steps of:
forming an isolation trench receiving therein an in-trench oxide film on a semiconductor substrate to separate an area of the semiconductor substrate into first through n-th circuit areas:
forming a first thermal oxide film having a largest thickness among the n different thicknesses in the first through n-th circuit areas; and
iterating, consecutively for i=2 to i=n, removing the first thermal oxide film in the i-th circuit area and forming an i-th thermal oxide film having an i-th largest thicknesses among the n different thickness in the i-th circuit area.
The present invention also provides, in a second aspect thereof, a method for fabricating a semiconductor device including gate oxide films having n different thicknesses, given n being an integer not smaller than three, the method including the steps of:
forming an isolation trench on a semiconductor substrate to separate an area of the semiconductor substrate into first through n-th circuit areas:
filling the trench with a filling member so that the filling member has a top surface higher than a top surface of the semiconductor substrate;
forming a first gate oxide film having a largest thickness among the n different thicknesses in the first through n-th circuit areas; and
iterating, consecutively for i=2 to i=n, removing the first gate oxide film in the i-th circuit area and forming an i-th gate oxide film having an i-th largest thickness among the n different thicknesses in the i-th circuit area.
The present invention also provides, in a third aspect thereof, a semiconductor device including:
a semiconductor substrate;
an isolation trench receiving therein an in-trench silicon oxide film and separating an area of the semiconductor substrate into first through n-th circuit areas; and
first through n-th thermal silicon oxide films formed in the first through n-th circuit areas, respectively, the first through n-th thermal silicon oxide films having first through n-th largest thicknesses, respectively,
the in-trench silicon oxide film having a top surface higher than a top surface of the semiconductor substrate in the first circuit area, the in-trench silicon oxide film having a top surface substantially flush with the top surface of the semiconductor substrate in the second through n-th circuit areas.
The present invention also provides, in a fourth aspect thereof, a semiconductor device including:
a semiconductor substrate;
an isolation trench filled with a filling member and separating an area of the semiconductor substrate into first through n-th circuit areas; and
first through n-th gate insulating films formed in the first through n-th circuit areas, respectively, the gate insulating films having first through n-th largest thicknesses, respectively,
the filling member having a top surface higher than a top surface of the semiconductor substrate in the first circuit area, the filling member having a top surface substantially flush with the top surface of the semiconductor substrate in the second through n-th circuit areas.
In accordance with the method of the present invention and the method for manufacturing the semiconductor device of the present invention, by consecutively forming silicon thermal oxide films so that the thermal oxide film having a largest thickness among the thicknesses of the remaining films, the process alleviates the influence on the thicknesses of the previous thermal oxide films by the later thermal oxidation, the previous thermal oxide films being formed by previous thermal oxidation steps. This allows the thermal oxide films in the resultant semiconductor device to have more accurate thicknesses.
In the method of the present invention, the circuit area is not limited to a specific area, and may be typically a MOS area wherein at least one MOSFET or at least a pair of MOSFETs is formed. In the MOS area, the thermal oxide films are gate insulating films or gate oxide films of the MOSFETs.
In the method of the present invention, since the thickness of the gate insulating film is varied depending on the desired characteristics of the MOSFET, the MOSFETs formed by the method are adapted to the variety of applications. The circuit area recited in the semiconductor device of the present invention may be a MOS area wherein at least one MOSFET or at least a pair of MOSFETs are formed, or a specific circuit area wherein a circuit having a specific function or at least one circuit element having a specific function is formed.
In the present invention, the term xe2x80x9cgate insulating filmxe2x80x9d may be typically a silicon oxide film, but not limited thereto, and may be a silicon oxide nitride film instead.
The first through n-th thermal oxide films in the present invention are typically gate insulating films; however, the thermal oxide films are not limited thereto. The in-trench oxide film may be replaced by another filling member such as a layer structure including a silicon oxide film, a silicon nitride film and a silicon oxide film.